\doxysection{MDMA\+\_\+\+Channel\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_m_d_m_a___channel___type_def}{}\label{struct_m_d_m_a___channel___type_def}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a5a5efbf83f104427b927e6b207cf26d1}{CISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a33065aa1d54e1aba74570382f7e367d4}{CIFCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a9811369e1b621b63eff14f3a50986062}{CESR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a835c47def48257f36879ad0ff5e3bb8e}{CCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a17b5ca2bff81a3b7ffffd4b3471973ae}{CTCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_ad27a6cee3f90bb9221cc993a6d4c10c3}{CBNDTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a9b845a89d1c4dec3e6df2d443955c0d8}{CSAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_aa79c99d83c06c265c094b0e2bb462993}{CDAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a94503b7dc3f8d03923ecf4376b5956a9}{CBRUR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a5b6aba31216cd09145878456e935262d}{CLAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a68b30850de97b936637d53508be9fdf2}{CTBR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_affaa311e2adf5e9186bf62e3f9763aee}{RESERVED0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_a78006e734147831c891244e439493d8f}{CMAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_m_d_m_a___channel___type_def_acbc1a147afb2fd72925a88697447993c}{CMDR}}
\end{DoxyCompactItemize}


\label{doc-variable-members}
\Hypertarget{struct_m_d_m_a___channel___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_m_d_m_a___channel___type_def_ad27a6cee3f90bb9221cc993a6d4c10c3}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CBNDTR@{CBNDTR}}
\index{CBNDTR@{CBNDTR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CBNDTR}{CBNDTR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_ad27a6cee3f90bb9221cc993a6d4c10c3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CBNDTR}

MDMA Channel x block number of data register, Address offset\+: 0x54 \Hypertarget{struct_m_d_m_a___channel___type_def_a94503b7dc3f8d03923ecf4376b5956a9}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CBRUR@{CBRUR}}
\index{CBRUR@{CBRUR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CBRUR}{CBRUR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a94503b7dc3f8d03923ecf4376b5956a9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CBRUR}

MDMA channel x Block Repeat address Update register, Address offset\+: 0x60 \Hypertarget{struct_m_d_m_a___channel___type_def_a835c47def48257f36879ad0ff5e3bb8e}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CCR@{CCR}}
\index{CCR@{CCR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR}{CCR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a835c47def48257f36879ad0ff5e3bb8e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CCR}

MDMA channel x control register, Address offset\+: 0x4C \Hypertarget{struct_m_d_m_a___channel___type_def_aa79c99d83c06c265c094b0e2bb462993}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CDAR@{CDAR}}
\index{CDAR@{CDAR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CDAR}{CDAR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_aa79c99d83c06c265c094b0e2bb462993} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CDAR}

MDMA channel x destination address register, Address offset\+: 0x5C \Hypertarget{struct_m_d_m_a___channel___type_def_a9811369e1b621b63eff14f3a50986062}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CESR@{CESR}}
\index{CESR@{CESR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CESR}{CESR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a9811369e1b621b63eff14f3a50986062} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CESR}

MDMA Channel x error status register, Address offset\+: 0x48 \Hypertarget{struct_m_d_m_a___channel___type_def_a33065aa1d54e1aba74570382f7e367d4}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CIFCR@{CIFCR}}
\index{CIFCR@{CIFCR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CIFCR}{CIFCR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a33065aa1d54e1aba74570382f7e367d4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CIFCR}

MDMA channel x interrupt flag clear register, Address offset\+: 0x44 \Hypertarget{struct_m_d_m_a___channel___type_def_a5a5efbf83f104427b927e6b207cf26d1}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CISR@{CISR}}
\index{CISR@{CISR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CISR}{CISR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a5a5efbf83f104427b927e6b207cf26d1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CISR}

MDMA channel x interrupt/status register, Address offset\+: 0x40 \Hypertarget{struct_m_d_m_a___channel___type_def_a5b6aba31216cd09145878456e935262d}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CLAR@{CLAR}}
\index{CLAR@{CLAR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CLAR}{CLAR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a5b6aba31216cd09145878456e935262d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CLAR}

MDMA channel x Link Address register, Address offset\+: 0x64 \Hypertarget{struct_m_d_m_a___channel___type_def_a78006e734147831c891244e439493d8f}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CMAR@{CMAR}}
\index{CMAR@{CMAR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CMAR}{CMAR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a78006e734147831c891244e439493d8f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CMAR}

MDMA channel x Mask address register, Address offset\+: 0x70 \Hypertarget{struct_m_d_m_a___channel___type_def_acbc1a147afb2fd72925a88697447993c}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CMDR@{CMDR}}
\index{CMDR@{CMDR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CMDR}{CMDR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_acbc1a147afb2fd72925a88697447993c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CMDR}

MDMA channel x Mask Data register, Address offset\+: 0x74 \Hypertarget{struct_m_d_m_a___channel___type_def_a9b845a89d1c4dec3e6df2d443955c0d8}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CSAR@{CSAR}}
\index{CSAR@{CSAR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSAR}{CSAR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a9b845a89d1c4dec3e6df2d443955c0d8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CSAR}

MDMA channel x source address register, Address offset\+: 0x58 \Hypertarget{struct_m_d_m_a___channel___type_def_a68b30850de97b936637d53508be9fdf2}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CTBR@{CTBR}}
\index{CTBR@{CTBR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CTBR}{CTBR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a68b30850de97b936637d53508be9fdf2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CTBR}

MDMA channel x Trigger and Bus selection Register, Address offset\+: 0x68 \Hypertarget{struct_m_d_m_a___channel___type_def_a17b5ca2bff81a3b7ffffd4b3471973ae}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!CTCR@{CTCR}}
\index{CTCR@{CTCR}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CTCR}{CTCR}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_a17b5ca2bff81a3b7ffffd4b3471973ae} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CTCR}

MDMA channel x Transfer Configuration register, Address offset\+: 0x50 \Hypertarget{struct_m_d_m_a___channel___type_def_affaa311e2adf5e9186bf62e3f9763aee}\index{MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!MDMA\_Channel\_TypeDef@{MDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_m_d_m_a___channel___type_def_affaa311e2adf5e9186bf62e3f9763aee} 
uint32\+\_\+t MDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+RESERVED0}

Reserved, 0x6C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
